Senior SoC RTL Design Engineer

About us: Mythic has developed a unified hardware and software platform featuring its unique Mythic Analog Compute Engine (Mythic ACE™) to deliver revolutionary power, cost, and performance that shatters digital barriers preventing AI innovation at the edge. Mythic's unique technology makes it much easier and more affordable to deploy powerful AI solutions, from the data center to the edge device. The company has raised over USD 125M in a recent funding round, and has offices in Palo Alto (CA, USA), Austin (TX, USA) and in Bangalore (Karnataka, India).   About the role: Mythic is a fast-paced startup looking for individuals that enjoy wide-reaching and flexible roles. The primary responsibility for this position is digital RTL design of Mythic's chips, but we are looking for individuals with strong computer architecture knowledge as well.   You will be the owner of all aspects of design and development for system-level blocks which form the SoC infrastructure. You will need to contribute, and ideally, have great ownership of, the architecture, microarchitecture, and RTL for a large high-performance system. Additionally, beyond defining what functionality these blocks provide, you will help drive methodologies to establish and enable first-pass success of these chips.   Beyond digital RTL design for our novel chip architecture, this role also presents a unique opportunity to get involved with and learn more about state-of-the-art deep neural networks (DNNs). You will also be collaborating with the system architecture, software, DFT, and analog design teams at Mythic. Mythic is an equal opportunity and affirmative action employer. It ensures equal employment opportunity without discrimination or harassment based on race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity or expression, age, disability, national origin, marital or domestic/civil partnership status, genetic information, citizenship status, veteran status, or any other characteristic protected by law.   We look forward to reviewing your application! At Mythic, we pride ourselves in creating a culture where all employees feel valued and appreciated for the diverse perspectives and backgrounds they bring to the team. We aim to hire smart people, give them the resources they need to do their job well, and then leave the rest up to them. We celebrate individual differences and encourage people to be comfortable bringing their authentic selves to work. At the end of the day, we are committed to building a diverse workforce where everyone belongs. Mythic is an equal opportunity and affirmative action employer. It ensures equal employment opportunity without discrimination or harassment based on race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity or expression, age, disability, national origin, marital or domestic/civil partnership status, genetic information, citizenship status, veteran status, or any other characteristic protected by law. We look forward to reviewing your application! country: IN all locations: [Bangalore] commitment: Full-time department: Mythic India location: Bangalore team: System-on-Chip Here's the background we hope you have:: BS/MS/PhD in EE/CS/CSE 3+ years of industry experience RTL, microarchitecture, and architecture experience on advanced SoCs Experience with Design for Test (DFT) and Design for Debug (DFD) logic such as fuse controllers, memory BIST, scan dump, etc. Experience with clocking and reset methodologies Understanding of timing constraints The following would be nice to have, but is not required:: Experience working at startups Experience with RTL design for clock domain crossings Experience with Python or Ruby Experience working with a regression system Experience working with a revision control system Comfortable working from command line