Jobs — flint

Skill: uvm

83 jobs · 3ms

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Staff Engineer, ASIC Design Verification
samsungsemiconductor 6d ago
$163k – $253k
senior · on-site · full time · San Jose
c++ dft hbm systemverilog uvm
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Senior FPGA Verification Engineer
andurilindustries 8d ago
$146k – $194k
senior · on-site · full time · Costa Mesa
do-254 git linux makefile nix python +8
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Director, Design Verification
samsungsemiconductor 10d ago
$219k – $351k
director · on-site · full time · San Jose
c++ systemverilog uvm
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Design Verification, Forward Deployed Engineering
openai 16d ago
$162k – $302k
senior · remote · full time · San Francisco
python systemverilog verdi uvm vcs questa
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Senior Physical Design Engineer
espace 18d ago
$120k – $220k
senior · on-site · full time · Saratoga
cadence innovus cpf mentor calibre python synopsys icc2 synopsys icv +6
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Senior DV Engineer
espace 19d ago
$120k – $220k
senior · on-site · full time · Saratoga
bash perl python systemverilog uvm verilog
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Staff DV Engineer
espace 19d ago
$120k – $220k
staff · on-site · full time · Saratoga
c++ perl python systemverilog uvm verilog
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Principal DV Engineer
espace 19d ago
$120k – $220k
principal · on-site · full time · Saratoga
bash c++ perl python systemverilog uvm +1
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Digital Design Verification Engineer
olix 19d ago
$170k – $285k
senior · on-site · full time · Austin
cocotb eda jasper matlab python systemverilog +2
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Lead ASIC Design Verification Engineer (Starshield Satellite Engineering)
spacex 22d ago
$160k – $225k
lead · on-site · full time · Hawthorne
python git systemverilog uvm
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SoC Platform Engineer
espace 22d ago
$150k – $220k
senior · on-site · full time · Saratoga
ahb amba apb axi bash corstone +14
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Digital Verification Manager
olix 23d ago
$388k
senior · on-site · full time · Austin
assertions cdc coverage eda emulation formal +8
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Digital Verification Manager
olix 23d ago
£220k
senior · on-site · full time · Bristol
cdc emulation fpga rdc systemverilog uvm
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Hardware Engineer, Design Verification
normalcomputing 24d ago
$140k – $180k
senior · hybrid · full time · New York
jasper perl python systemverilog uvm vmanager +1
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FPGA Intern (Fall 2026)
astranis 24d ago
$29
intern · remote · internship ·
adc dac jesd204b ldpc systemverilog tcl +3
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FPGA Associate (Fall 2026)
astranis 24d ago
$1k
intern · on-site · internship · San Francisco
adc dac jesd204b ldpc systemverilog tcl +4
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ASIC Design Engineer, Senior
positron 27d ago
$225k – $350k
senior · remote · full time ·
ace axi chi cocotb ddr dft +6
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ASIC Design Verification Engineer
positron Apr 24, 2026
$200k – $350k
senior · remote · full time ·
ai inference asics cadence mentor graphics perl python synopsys +3
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Staff Engineer, CPU Core Verification
tenstorrent Apr 21, 2026
$100k – $500k
senior · hybrid · full time · Austin, Santa Clara
risc-v uvm
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Staff Engineer, SoC RTL Engineer
tenstorrent Apr 21, 2026
staff · hybrid · full time · Tokyo
risc-v uvm verilog vhdl
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Staff Engineer, ASIC Design Verification

Senior FPGA Verification Engineer

Director, Design Verification

Design Verification, Forward Deployed Engineering

Senior Physical Design Engineer

Senior DV Engineer

Staff DV Engineer

Principal DV Engineer

Digital Design Verification Engineer

Lead ASIC Design Verification Engineer (Starshield Satellite Engineering)

SoC Platform Engineer

Digital Verification Manager

Digital Verification Manager

Hardware Engineer, Design Verification

FPGA Intern (Fall 2026)

FPGA Associate (Fall 2026)

ASIC Design Engineer, Senior

ASIC Design Verification Engineer

Staff Engineer, CPU Core Verification

Staff Engineer, SoC RTL Engineer