ahb

Recent positions

• SoC Platform Engineer

  espace · 23d ago

  $150k – $220k

  senior · on-site · full time · Saratoga

  python git bash make tcl systemverilog +14
  Apply

• SoC Firmware Engineer

  espace · 23d ago

  $150k – $220k

  senior · on-site · full time · Saratoga

  python git bash jenkins rust i2c +20
  Apply

• Manager, ASIC Design Engineering (Starshield Silicon)

  spacex · 23d ago

  $190k – $245k

  manager · on-site · full time · Hawthorne

  python tcl verilog axi vcs vivado +3
  Apply

• Principal ASIC Design Engineer (Starshield)

  spacex · Apr 7, 2026

  $210k – $295k

  principal · on-site · full time · Palo Alto

  python tcl verilog axi vcs vivado +3
  Apply

• Sr. ASIC Design Engineer (Starshield)

  spacex · Apr 7, 2026

  $170k – $235k

  senior · on-site · full time · Palo Alto

  python tcl verilog axi vcs vivado +5
  Apply

• Sr. ASIC Design Engineer (Starshield)

  spacex · Apr 3, 2026

  $160k – $225k

  senior · on-site · full time · Irvine

  verilog axi vcs xilinx vivado altera +4
  Apply

• Principal ASIC Design Engineer (Starshield)

  spacex · Apr 3, 2026

  $200k – $285k

  principal · on-site · full time · Irvine

  python tcl verilog axi vcs xilinx +6
  Apply

• Principal ASIC Design Engineer (Starshield)

  spacex · Apr 3, 2026

  $200k – $285k

  principal · on-site · full time · Hawthorne

  verilog axi vcs xilinx vivado altera +4
  Apply

• Sr. ASIC Design Engineer (Starshield)

  spacex · Apr 3, 2026

  $160k – $225k

  senior · on-site · full time · Hawthorne

  verilog axi vcs xilinx vivado altera +4
  Apply

• RTL Design Engineer (Silicon Engineering)

  spacex · Mar 17, 2026

  $125k – $145k

  mid · on-site · full time · Irvine

  python verilog systemverilog axi apb ahb +1
  Apply

• Sr. RTL Design Engineer (Silicon Engineering)

  spacex · Mar 10, 2026

  $160k – $225k

  senior · on-site · full time · Irvine

  python verilog axi ahb hdl simulators hdl lint tools
  Apply

• ASIC Design Verification Engineer

  k2spacecorporation · Mar 10, 2026

  $130k – $200k

  mid · on-site · full time · Los Angeles

  python git perl tcl simvision systemverilog +10
  Apply

• Sr. ASIC Design Engineer (Silicon Engineering)

  spacex · Dec 22, 2025

  $170k – $235k

  senior · on-site · full time · Sunnyvale

  python tcl verilog axi vcs vivado +3
  Apply