systemverilog

Recent positions

• Senior Analog / Mixed-Signal IC Design Engineer

  psiquantum · 5d ago

  $145k – $165k

  senior · on-site · full time · Palo Alto

  verilog systemverilog adc dac tia spectre +2
  Apply

• Staff Engineer, ASIC Design Verification

  samsungsemiconductor · 6d ago

  $163k – $253k

  senior · on-site · full time · San Jose

  c++ systemverilog hbm dft uvm
  Apply

• Senior FPGA Verification Engineer

  andurilindustries · 8d ago

  $146k – $194k

  senior · on-site · full time · Costa Mesa

  linux python git do-254 tcl systemverilog +8
  Apply

• Staff Engineer, FPGA

  samsungsemiconductor · 10d ago

  $163k – $253k

  senior · on-site · full time · San Jose

  pci verilog systemverilog axi vcs vivado +5
  Apply

• Director, Design Verification

  samsungsemiconductor · 11d ago

  $219k – $351k

  director · on-site · full time · San Jose

  c++ systemverilog uvm
  Apply

• Principal ASIC Design Engineer

  atomcomputing · 12d ago

  $180k – $220k

  principal · on-site · full time · Austin, Boulder

  fpga systemverilog cadence synopsys microprocessor
  Apply

• OS Platform Engineer

  k2spacecorporation · 12d ago

  $160k – $200k

  mid · on-site · full time · Los Angeles

  linux c++ python yocto rust systemverilog +5
  Apply

• Sr. FPGA Engineer

  chaosindustries · 13d ago

  $160k – $225k

  senior · on-site · full time · Los Angeles

  python git bash jenkins i2c spi +10
  Apply

• Senior/Staff Digital Design Engineer

  olix · 13d ago

  senior · on-site · full time · Austin

  python matlab simulink fpga numpy verilog +4
  Apply

• Design Verification, Forward Deployed Engineering

  openai · 16d ago

  $162k – $302k

  senior · remote · full time · San Francisco

  python systemverilog verdi uvm vcs questa
  Apply

• Senior FPGA Engineer

  akunacapital · 16d ago

  $145k

  senior · on-site · full time · Chicago

  python bash verilog systemverilog
  Apply

• Senior ASIC Design Engineer – Processor Subsystem

  espace · 16d ago

  $150k – $220k

  senior · on-site · full time · Saratoga

  python perl tcl systemverilog upf arm +4
  Apply

• SoC Power Architecture Engineer - Processor Subsystem

  espace · 16d ago

  $150k – $220k

  senior · on-site · full time · Saratoga

  systemverilog upf arm vhdl amba
  Apply

• Senior Physical Design Engineer

  espace · 18d ago

  $120k – $220k

  senior · on-site · full time · Saratoga

  python tcl verilog systemverilog upf uvm +6
  Apply

• FPGA / VLSI Engineer

  espace · 18d ago

  $120k – $220k

  mid · on-site · full time · Saratoga

  fpga verilog systemverilog soc asic
  Apply

• FPGA Engineering Manager

  NorthwoodSpace · 19d ago

  $208k – $304k

  manager · on-site · full time · Torrance

  python networking systemverilog dsp vhdl schematic +1
  Apply

• Senior DV Engineer

  espace · 19d ago

  $120k – $220k

  senior · on-site · full time · Saratoga

  python bash perl verilog systemverilog uvm
  Apply

• Staff DV Engineer

  espace · 19d ago

  $120k – $220k

  staff · on-site · full time · Saratoga

  c++ python perl verilog systemverilog uvm
  Apply

• Principal DV Engineer

  espace · 19d ago

  $120k – $220k

  principal · on-site · full time · Saratoga

  c++ python bash perl verilog systemverilog +1
  Apply

• Senior/Staff Design for Test Engineer

  olix · 19d ago

  senior · on-site · full time · Bristol

  python tcl verilog systemverilog jtag vhdl +10
  Apply