Sr Staff /Staff DFT Engineer

About us: Mythic has developed a unified hardware and software platform featuring its unique Mythic Analog Compute Engine (Mythic ACE™) to deliver revolutionary power, cost, and performance that shatters digital barriers preventing AI innovation at the edge. Mythic's unique technology makes it much easier and more affordable to deploy powerful AI solutions, from the data center to the edge device. The company has raised over USD 125M in a recent funding round and has offices in Palo Alto (CA, USA), Austin (TX, USA), and Bangalore (Karnataka, India). About This Role: Mythic is a fast-paced startup looking for individuals that enjoy wide-reaching and flexible roles. The primary responsibility for this position is implementaiton of DFT features on Mythic's chips.  You will lead end-to-end Design for Testability (DFT) implementation, verification for complex ASIC/SoC designs. You will own all aspects of DFT for SoC such as MBIST, IJTAG, Scan and ATPG . You will also contribute significantly to DFT methodologies to establish flow for all DFT features like MBIST,SCAN and ATPG and enable first-pass success of these chips. You are expected to be involved and contribute to every phase of the design cycle from Concept to Silicon. Beyond DFT for our novel chip architecture, this role also presents a unique opportunity to get involved with and learn more about state-of-the-art deep neural networks (DNNs). You will also be collaborating with the RTL design , Physical design, STA and analog design teams at Mythic. At Mythic, we pride ourselves in creating a culture where all employees feel valued and appreciated for the diverse perspectives and backgrounds they bring to the team. We aim to hire smart people, give them the resources they need to do their job well, and then leave the rest up to them. We celebrate individual differences and encourage people to be comfortable bringing their authentic selves to work. At the end of the day, we are committed to building a diverse workforce where everyone belongs. Mythic is an equal opportunity and affirmative action employer. It ensures equal employment opportunity without discrimination or harassment based on race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity or expression, age, disability, national origin, marital or domestic/civil partnership status, genetic information, citizenship status, veteran status, or any other characteristic protected by law. We look forward to reviewing your application! country: IN all locations: [Bangalore] commitment: Full-time department: Mythic India location: Bangalore team: System-on-Chip Here is what you will do:: BS/MS/PhD in EE/ECEAt least 8+ years of industry experienceSoC level experience in DFT methodologies (e.g. Memory Repair, Hierarchical DFT, IEEE 1687 iJTAG, Scan, ATPG, Memory BIST.Experience with SoC Level DFT Integration, Verification, DFT test suite development and RTL design for DFT.Experience with SoC Level DFT Integration, Verification and RTL design for DFTExperience with DFT strategies like Scan insertion, TPI, SSN, Hierarchical DFT and ATPGPre-Silicon test planning & verification strategyKnowledge & experience of low power concepts, clock gating, power gating is a plusAdept at root cause analysis and resolving DFT implementation issuesMust have good communication skills and the ability to work in a worldwide team environmentA past experience of working on an AI processor design is a huge plus. Here is the background we hope you have:: Experience working at startupsKnowledge of Low power DFT solutionsExperience of working with STA team to define DFT timing constraintsWorking with ATE (Automatic Test Equipment) for bring-up, debugging, and yield improvementProficiency in Synopsys (TetraMAX/DFT Compiler) or Siemens/Mentor (Tessent) tools, Verilog/SystemVerilogGood script skills including Perl, Tcl, Python, etc. The following would be nice to have, but is not required: : Knowledge of chiplet-based design limitations and their impact on physical design.Experience in Sub-10nm designsFamiliarity and hands-on experience with Cadence toolsets.