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systemverilog 155 python 89 verilog 76 uvm 63 vhdl 39 c++ 31 tcl 24 matlab 22 linux 19 git 15+240 more

Seniority

senior 86 mid 26 principal 12 intern 8 staff 7 director 5 unknown 4 manager 3+2 more

Category

engineering 154 other 1

Modality

on site 115 hybrid 23 remote 17

Employment

full time 144 internship 9 unknown 2

Countries

US 120 GB 11 IN 8 NL 5 CA 4 FR 3 DE 3 IT 2 CH 2 BE 2 KR 1 JP 1 IL 1 IE 1 AU 1

Cities

Austin 24 Saratoga 13 San Jose 12 Palo Alto 12 Los Angeles 10 Bristol 7 Hawthorne 6 Santa Clara 6+40 more

Salary (USD/yr)

–

Amount in thousands. e.g. 120 = $120k

Skill: systemverilog

155 jobs · 5ms

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Staff Engineer, ASIC Design Verification
samsungsemiconductor 6d ago
$163k – $253k
senior · on-site · full time · San Jose
c++ dft hbm systemverilog uvm
Apply
Senior FPGA Verification Engineer
andurilindustries 9d ago
$146k – $194k
senior · on-site · full time · Costa Mesa
do-254 git linux makefile nix python +8
Apply
Staff Engineer, FPGA
samsungsemiconductor 11d ago
$163k – $253k
senior · on-site · full time · San Jose
axi axis cxl pci quartus questa +5
Apply
Director, Design Verification
samsungsemiconductor 11d ago
$219k – $351k
director · on-site · full time · San Jose
c++ systemverilog uvm
Apply
Principal ASIC Design Engineer
atomcomputing 13d ago
$180k – $220k
principal · on-site · full time · Austin, Boulder
cadence fpga microprocessor synopsys systemverilog
Apply
OS Platform Engineer
k2spacecorporation 13d ago
$160k – $200k
mid · on-site · full time · Los Angeles
bitbake buildroot c++ linux ptp python +5
Apply
Sr. FPGA Engineer
chaosindustries 14d ago
$160k – $225k
senior · on-site · full time · Los Angeles
axi bash can git i2c ip +10
Apply
Senior/Staff Digital Design Engineer
olix 14d ago
senior · on-site · full time · Austin
fpga intel matlab numpy python simulink +4
Apply
Design Verification, Forward Deployed Engineering
openai 16d ago
$162k – $302k
senior · remote · full time · San Francisco
python systemverilog verdi uvm vcs questa
Apply
Senior FPGA Engineer
akunacapital 16d ago
$145k
senior · on-site · full time · Chicago
bash python systemverilog verilog
Apply
Senior ASIC Design Engineer – Processor Subsystem
espace 17d ago
$150k – $220k
senior · on-site · full time · Saratoga
amba arm cadence xcelium perl python synopsys vcs +4
Apply
SoC Power Architecture Engineer - Processor Subsystem
espace 17d ago
$150k – $220k
senior · on-site · full time · Saratoga
amba arm systemverilog upf vhdl
Apply
Senior Physical Design Engineer
espace 18d ago
$120k – $220k
senior · on-site · full time · Saratoga
cadence innovus cpf mentor calibre python synopsys icc2 synopsys icv +6
Apply
FPGA / VLSI Engineer
espace 19d ago
$120k – $220k
mid · on-site · full time · Saratoga
asic fpga soc systemverilog verilog
Apply
FPGA Engineering Manager
NorthwoodSpace 19d ago
$208k – $304k
manager · on-site · full time · Torrance
dsp networking python schematic systemverilog vhdl +1
Apply
Senior DV Engineer
espace 20d ago
$120k – $220k
senior · on-site · full time · Saratoga
bash perl python systemverilog uvm verilog
Apply
Staff DV Engineer
espace 20d ago
$120k – $220k
staff · on-site · full time · Saratoga
c++ perl python systemverilog uvm verilog
Apply
Principal DV Engineer
espace 20d ago
$120k – $220k
principal · on-site · full time · Saratoga
bash c++ perl python systemverilog uvm +1
Apply
Senior/Staff Design for Test Engineer
olix 20d ago
senior · on-site · full time · Bristol
atpg bring-up compression diagnosis eda edt +10
Apply
Digital Design Verification Engineer
olix 20d ago
$170k – $285k
senior · on-site · full time · Austin
cocotb eda jasper matlab python systemverilog +2
Apply

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