synthesis

Recent positions

• Consultant - Cultural & Creative Sector

  strategicgears · 12d ago

  $120k – $150k

  mid · on-site · full time · Riyadh

  management consulting synthesis structured problem-solving interview execution cultural consulting creative-sector intuition +6
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• ASIC Design Engineer, Senior

  positron · 27d ago

  $225k – $350k

  senior · remote · full time

  systemverilog hbm dft uvm cocotb risc-v +6
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• Power Performance Architect, Senior Staff - Accelerator Design

  d-Matrix · Apr 9, 2026

  $160k – $235k

  staff · hybrid · full time · Santa Clara

  python tcl dvfs rtl asic eda +7
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• Senior Automation/Medicinal Chemist

  recursionpharmaceuticals · Apr 2, 2026

  £70k – £93k

  senior · on-site · full time · Milton Park

  automation chemistry drug discovery synthesis medicinal chemistry
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• Digital Design Engineer, Micro-Architect, Principal

  d-Matrix · Mar 3, 2026

  $180k – $300k

  principal · hybrid · full time · Santa Clara

  cad verilog rtl digital architecture design +12
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• Sr Staff Engineer, CPU System Microarchitect

  tenstorrent · Mar 2, 2026

  $1600k – $2500k

  senior · hybrid · full time · Bengaluru

  verilog risc-v simulation vhdl synthesis power analysis
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• RTL & Co-design Engineer (junior)

  openai · Jan 22, 2026

  $225k – $445k

  junior · hybrid · full time · San Francisco

  ml lint verilog rdc systemverilog cdc +2
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• Principal Compute Architect

  foundation-robotics · Dec 2, 2025

  $180k – $300k

  principal · on-site · full time · San Francisco

  hardware security fpga embedded verilog rtl +14
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• RTL & Codesign Engineer

  openai · Nov 20, 2025

  $225k – $445k

  senior · hybrid · full time · San Francisco

  lint verilog rdc systemverilog cdc sta +1
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• Staff Silicon Physical Design Engineer - Bengaluru

  graphcore · Nov 12, 2025

  INR 12000k – INR 15000k

  senior · on-site · full time · Bengaluru

  python tcl eda cts synthesis lvs +4
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• High Speed Interface(IO) Design Engineer

  furiosa-ai · Oct 3, 2025

  senior · remote · full time · Seoul

  ethernet fpga rtl hbm lpddr verification +2
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