Senior Digital Verification Engineer

About us: Mythic has developed a unified hardware and software platform featuring its unique Mythic Analog Compute Engine (Mythic ACE™) to deliver revolutionary power, cost, and performance that shatters digital barriers preventing AI innovation at the edge. The Mythic Analog Matrix Processor (Mythic AMP™) makes it much easier and more affordable to deploy powerful AI solutions, from the data center to the edge device. The company has raised a fresh round of funding, and has offices in Palo Alto, CA, and Austin, TX. About the role: We are seeking Verification Engineers to work on the verification of complex digital IPs and AI SoC design. This role involves developing and executing SystemVerilog/UVM-based verification environments, debugging functional issues, and collaborating closely with RTL design teams to ensure first-time-right silicon. Mythic is an equal opportunity and affirmative action employer. It ensures equal employment opportunity without discrimination or harassment based on race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity or expression, age, disability, national origin, marital or domestic/civil partnership status, genetic information, citizenship status, veteran status, or any other characteristic protected by law. We look forward to reviewing your application! At Mythic, we pride ourselves in creating a culture where all employees feel valued and appreciated for the diverse perspectives and backgrounds they bring to the team. We aim to hire smart people, give them the resources they need to do their job well, and then leave the rest up to them. We celebrate individual differences and encourage people to be comfortable bringing their authentic selves to work. At the end of the day, we are committed to building a diverse workforce where everyone belongs. Mythic is an equal opportunity and affirmative action employer. It ensures equal employment opportunity without discrimination or harassment based on race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity or expression, age, disability, national origin, marital or domestic/civil partnership status, genetic information, citizenship status, veteran status, or any other characteristic protected by law. We look forward to reviewing your application! country: IN all locations: [Bangalore] commitment: Full-time department: Mythic India location: Bangalore team: System-on-Chip Here is what you will do: Hands-on system-level and block-level verification. Development of test plans and coverage plans. Testbench development and execution using UVM or other advanced DV methodologies. Creation of verification infrastructure and flows. Leverage architecture models to help verify large AI network functionality on the design. Collaborate with RTL designers and architects to verify subsystems such as scheduling fabrics, interconnects, DMA engines, and memory controllers. Here's the background we hope you have:: Bachelor’s, Master’s, or Ph.D. degree in Electrical Engineering,. 5+ years of industry experience developing verification testbenches. Knowledge of verification methodologies (UVM or similar). Solid understanding of computer architecture, including datapaths, memory hierarchies, and interconnects. Experience verifying one or more of the following: scheduling subsystems, high-performance interconnects, DMA engines, or memory subsystems. Understanding of Verilog, SystemVerilog, and UVM. Knowledge of coverage-driven verification and advanced stimulus generation techniques. Proven track record of first-pass silicon success. Strong communication skills, both written and spoken.   The following would be nice to have, but is not required:: Exposure to formal verification methods and tools. Familiarity with power-aware and performance-driven verification flows. Prior experience verifying AI, DSP, or other highly parallel architectures. Strong scripting skills (Python or similar) for automation and infrastructure development.